Quote Originally Posted by wthomas View Post
Ahh thats very similar to VDHL that i know of. But as its a hardware language, i don't think it would support that arrays like that. From what I know of Verilog, its used for a programmatic display/simulation of an electronic circuit. Are you designing a hardware sudoku solver?
from some research it looks like the newer Verilog versions support 2D but my professor said the version we have doesnt. and ya, thats right on the money. im using an FPGA that will allow the user to input the suduko size, the given values for the cells, a reset, enter, and solve. if we have enough time we're going to try and output it on a monitor which would be pretty badass. but by using C, if my understanding is right, we can make an arry of the sudukos x-columns and y-rows, and then combine those two arrays into one where each column has a corresponding row and cells within. how we would communicate that new 1d array- still trying to figure it out if this is even possible lol