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Thread: Verilog 32 Bit Processor

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    Default Verilog 32 Bit Processor

    Ok, so verilog is a hardware development language, which means i can write a program to create actual hard ware. Yeah, i know, funny how that works. But, hers the scoop, I need to program me a processor, and it needs to be able to handle most mips (assembly language) commands.

    So far, it compiles, lol, and might work. I need to make a test bench, i dont need help, and this is just for some people to look at and say "wow, thats cool, im glad i dont have to do that"

    oh yeah, its a piplined processor, but thats about as good as it gets, everyhting else is basic and simple and just.. low performance.
    SCAR Code:
    `timescale 1ns / 1ps
    //////////////////////////////////////////////////////////////////////////////////
    // Company:  World Domination
    // Engineer: Greg Hendrickson
    //
    // Create Date:    23:09:34 11/03/2007
    // Design Name:     Pipelined CPU Stage 1
    // Module Name:    CPU
    // Project Name:    Comp Arch Final Project
    // Target Devices: Desktop
    // Tool versions:
    // Description:
    //
    // Dependencies:
    //
    // Revision:
    // Revision 0.01 - File Created
    // Revision 0.02 - Syntax errors fixed
    // Revision 0.03 - Logical Errors Fixed
    // Revision 0.04 - Rest of code understood
    // Revision 0.05 - Added in and understood forwarding the a and b
    // Revision 0.06 - Could not find any errors in the forwarding code
    // Revision 0.07 - Added in the stalls
    // Revision 0.08 - Fixed minor "no-op" syntax error
    // Revision 0.09 - Found and fixed instruction forwarding error.  Cant do all at end (stall fails)
    // Additional Comments:
    //
    //////////////////////////////////////////////////////////////////////////////////
    module CPU (clock);
        // Instruction opcodes
        parameter LW = 6'b100011, SW = 6'b101011, BEQ=6'b000100, noop = 32'b00000_100000, ALUop=6''b0;
        input clock;
        reg[31:0] PC, Regs[0:31], IMemory[0:23], DMemory[0:23], // separate memories (they were 1023, i made them, 23)
        IFIDIR, IDEXA, IDEXB, IDEXIR, EXMEMIR, EXMEMB, // pipeline registers
        EXMEMALUOut, MEMWBValue, MEMWBIR; // pipeline registers
        wire [4:0] IDEXrs, IDEXrt, EXMEMrd, MEMWBrd, MEMWBrt; // Access register fields
        wire [5:0] EXMEMop, MEMWBop, IDEXop; // Access opcodes
        wire [31:0] Ain, Bin; // the ALU inputs
        // declare the bypass signals
        wire bypassAfromMEM, bypassAfromALUinWB,bypassBfromMEM, bypassBfromALUinWB,
        bypassAfromLWinWB, bypassBfromLWinWB;  
       
        // These assignment define fields from the pipeline registers
        assign IDEXrs = IDEXIR[25:21]; // rs field
        assign IDEXrt = IDEXIR[15:11]; // rt field
        assign EXMEMrd = EXMEMIR[15:11]; // rd field
        assign MEMWBrd = MEMWBIR[15:11]; //rd field [changed from 20;16] TO  15;11 //double checked, yes
        assign MEMWBrt = MEMWBIR[25:20]; //rt field--used for loads
        assign EXMEMop = EXMEMIR[31:26]; // the opocde
        assign MEMWBop = MEMWBIR[31:26]; // the opcode
        assign IDEXop = IDEXIR[31:26] ; // the opcode
        // Inputs to the ALU come directly from the ID/EX pipeline registers
        assign Ain = IDEXA;
        assign Bin = IDEXB;
       
        // The bypass to input A from the MEM stage for an ALU operation
        assign bypassAfromMEM = (IDEXrs == EXMEMrd) & (IDEXrs!=0) & (EXMEMop==ALUop); // yes, bypass
        // The bypass to input Bfrom the MEM stage for an ALU operation
        assign bypassBfromMEM = (IDEXrt== EXMEMrd)&(IDEXrt!=0) & (EXMEMop==ALUop); // yes, bypass
        // The bypass to input A from the WB stage for an ALU operation
        assign bypassAfromALUinWB =( IDEXrs == MEMWBrd) & (IDEXrs!=0) & (MEMWBop==ALUop);
        // The bypass to input B from the WB stage for an ALU operation
        assign bypassBfromALUinWB = (IDEXrt==MEMWBrd) & (IDEXrt!=0) & (MEMWBop==ALUop);
        // The bypass to input A from the WB stage for an LW operation
        assign bypassAfromLWinWB =( IDEXrs ==MEMWBIR[20:16]) & (IDEXrs!=0) & (MEMWBop==LW);
        // The bypass to input B from the WB stage for an LW operation
        assign bypassBfromLWinWB = (IDEXrt==MEMWBIR[20:16]) & (IDEXrt!=0) & (MEMWBop==LW);
        // The A input to the ALU is bypassed from MEM if there is a bypass there,
        // Otherwise from WB if there is a bypass there, and otherwise comes from the IDEX register
        assign Ain = bypassAfromMEM? EXMEMALUOut :
        (bypassAfromALUinWB | bypassAfromLWinWB)? MEMWBValue : IDEXA;
        // The B input to the ALU is bypassed from MEM if there is a bypass there,
        // Otherwise from WB if there is a bypass there, and otherwise comes from the IDEX register
        assign Bin = bypassBfromMEM? EXMEMALUOut :
        (bypassBfromALUinWB | bypassBfromLWinWB)? MEMWBValue: IDEXB;
       
        // The signal for detecting a stall based on the use of a result from LW
        assign stall = (MEMWBIR[31:26]==LW) && // source instruction is a load
        ((((IDEXop==LW)|(IDEXop==SW)) && (IDEXrs==MEMWBrd)) | // stall for address calc
        ((IDEXop==ALUop) && ((IDEXrs==MEMWBrd)|(IDEXrt==MEMWBrd)))); // ALU use
       
        reg [5:0] i; //used to initialize registers
        initial begin
            PC = 0;
            IFIDIR=noop; IDEXIR=noop; EXMEMIR=noop; MEMWBIR=noop; // put no-ops in pipeline registers
            for (i=0;i<=31;i=i+1) Regs[i] = i; //initialize registers--just so they aren?t cares
        end
        always @ (posedge clock) begin
            // Remember that ALL these actions happen every pipestage and with the use of <= they happen in parallel!
            // first instruction in the pipeline is being fetched
           
            if (~stall) begin // the first three pipeline stages stall if there is a load hazard
                    IFIDIR <= IMemory[PC>>2];
                    PC <= PC + 4;
                //end // Fetch & increment PC
               
                // second instruction in pipeline is fetching registers
                    IDEXA <= Regs[IFIDIR[25:21]]; IDEXB <= Regs[IFIDIR[20:16]]; // get two registers
                   
                // third instruction is doing address calculation or ALU operation
                if ((IDEXop==LW) |(IDEXop==SW)) // address calculation
                    EXMEMALUOut <= IDEXA +{{16{IDEXIR[15]}}, IDEXIR[15:0]};
                else if (IDEXop==ALUop) case (IDEXIR[5:0]) //case for the various R-type instructions
                    32: EXMEMALUOut <= Ain + Bin; //add operation
                    16: EXMEMALUOut <= Ain - Bin; //subtract operation
                    8:  EXMEMALUOut <= Ain & Bin; //and operation
                    7:  EXMEMALUOut <= ~(Ain & Bin); //nadd operation
                    4:  EXMEMALUOut <= Ain | Bin; //or operation
                    3:  EXMEMALUOut <= ~(Ain | Bin); //nor operation
                    2:  EXMEMALUOut <= ((Ain - Bin)==0)?1:0; //seqz operation
                    1:  EXMEMALUOut <= Ain < Bin ? 1:0; //slt operation
                    default: ; //other R-type operations: subtract, SLT, etc.
                endcase
               
                IDEXIR <= IFIDIR; EXMEMIR <= IDEXIR; EXMEMB <= IDEXB;// passing along instructions
           
            end
            else EXMEMIR <= noop; //Freeze first three stages of pipeline; inject a nop into the EX output
               
            //Mem stage of pipeline
            if (EXMEMop==ALUop)
                MEMWBValue <= EXMEMALUOut; //pass along ALU result
            else if (EXMEMop == LW)
                MEMWBValue <= DMemory[EXMEMALUOut>>2];
            else if (EXMEMop == SW)
                DMemory[EXMEMALUOut>>2] <=EXMEMB; //store [from top, it is 15:0)stage3
           
            // the WB stage
            if ((MEMWBop==ALUop) & (MEMWBrd != 0)) // update registers if ALU operation and destination not 0
                Regs[MEMWBrd] <= MEMWBValue; // ALU operation
            else if ((EXMEMop == LW)& (MEMWBrt != 0)) // Update registers if load and destination not 0
                Regs[MEMWBrt] <= MEMWBValue;
           
           
            MEMWBIR <= EXMEMIR; //pass along
            end
           
           
    endmodule
    [IMG]http://farm3.static.flickr.com/2120/2052732965_348f3629d0_o.jpg[/IMG]

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    Before you program a processor, go look into PIC processors and get yourself one. Then you will have your questions answered.


    Anyway, that looks a lot like basic. Go be 1337 and google Assembly.
    The jealous temper of mankind, ever more disposed to censure than
    to praise the work of others, has constantly made the pursuit of new
    methods and systems no less perilous than the search after unknown
    lands and seas.

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    Quote Originally Posted by R0b0t1 View Post
    Before you program a processor, go look into PIC processors and get yourself one. Then you will have your questions answered.


    Anyway, that looks a lot like basic. Go be 1337 and google Assembly.
    Yep, I am using the xilinx ISE to work with this verilog code. It takes it and sysnthesizes it, and eventually can map it onto an assortment of programable chips. I have done some simple stuff like that before, (making a math unit, a multiplier, etc).

    This project is just a little bit harder for me at least, because it is much more high level. I am relying on verilog to create the cookie cutter hardware that I need (like the alu) other than making it myself.

    And yeah, assembly is something I have already been doing. I did mips usui9ng the spim simulator to test it, but I have looked at other assembly code (like some of photshops, etc) and it is all about the same thing.

    This code right here will never be put onto a chip though, its mainly just for teaching purposes and to help me prove that i understand how a pipelines procesor works, and how to deal with the problems with it (forwarding and stalls, etc)

    The most I will do with it is make a test bench for it and send it through a simulator , and have it run a little bit of assembly to make sure it works.
    [IMG]http://farm3.static.flickr.com/2120/2052732965_348f3629d0_o.jpg[/IMG]

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    Wow, well done! I don't care how simple verilog is supposed to be, I could never do that. I'm not very good with hardware building the way I am with software building.

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    Quote Originally Posted by Nontitle View Post
    Wow, well done! I don't care how simple verilog is supposed to be, I could never do that. I'm not very good with hardware building the way I am with software building.
    well, if you really get down and dirty with it, the amount of logic that verilog takes care of is impresive. Writing a page of code is MUCH better than creating this by hand. We are tlaking HUNDREDS of parts. Trust me, ive been there, even creating a little 4 bit counter turns into a zombie looking nightmare. (debugging is even funner)

    But yeah, im still working on that code, allot of it i got from various examples and such, (and allot of them had errors... grr) but I starting to iron it out.

    (specialy wqhen you consider it it due teusday)

    Right now Xilinx (which you can dl for free if you google "xilinx ise") if giving me syntax errors somewhere in my test bench...


    Well, once it is all done, (or substantially diferent than what I have posted) ill make updates, and even include some pretty test bench pictures for you.
    [IMG]http://farm3.static.flickr.com/2120/2052732965_348f3629d0_o.jpg[/IMG]

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    OOOh Pretty pictures


    I always thought making my own chips would be fun, but I've never gotten the stuff.
    The jealous temper of mankind, ever more disposed to censure than
    to praise the work of others, has constantly made the pursuit of new
    methods and systems no less perilous than the search after unknown
    lands and seas.

  7. #7
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    does that mean that u could, say...program urself a videocard so u could display graphics that ur current 1 couldnt? or am i missing the point
    SCAR Tutorials: The Form Tutorial | Types, Arrays, and Classes
    Programming Projects: NotePad | Tetris | Chess


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    Quote Originally Posted by dan cardin View Post
    does that mean that u could, say...program urself a videocard so u could display graphics that ur current 1 couldnt? or am i missing the point
    yeah, knda missing the point, but not all the way.

    Verilog is a hardware descriptoon language. You can basically describe how you want any pice of hardware to be made.

    You can do it lower lever, by ac tualy describing each gate you want to have, or you can describe it high level (like i did) and just use logical if and assignment statments to do everyhting.

    Eventauly, this all gets systhesized down to the hardware level, and then programed onto a chip.

    Now, i would like to emphasise that this is mainly just fro programing chips that are made to be programed, or for generating a schematic.

    A video card is a very advanced, and very .. efficant piece of hardware. The top manuafucturesr would NEVER use the high level stuff like I did, aas it is slow and poorly designed. They have their own enginers personally develop all of the chips that they need.

    Now, there are a few chips on your vidio card, and thoese pretty much have to be programed at some point, so yes, they would use somehting like xilinx to do that for them.

    What i made was really nothing but a demonstration. It isnt a real processor, it just works and runs exactly like a pipeline proccesor would. Everyhting in this is just for demonstration and simulation, only for learning basically.
    [IMG]http://farm3.static.flickr.com/2120/2052732965_348f3629d0_o.jpg[/IMG]

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    ohhh...i thought u meant u could make like a virtual computer that u could run, kinda like a vm-ish thing then u could do stuff

    oh well
    SCAR Tutorials: The Form Tutorial | Types, Arrays, and Classes
    Programming Projects: NotePad | Tetris | Chess


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    Actually, dan, some CS:S people got in a huff because someone figured out how to write a graphics driver that made the walls semi-transparent. No hacks, so VAC didn't find it.

    Interesting Info FTW.
    The jealous temper of mankind, ever more disposed to censure than
    to praise the work of others, has constantly made the pursuit of new
    methods and systems no less perilous than the search after unknown
    lands and seas.

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    thats awsome oo bad i dont know that guy

    so could u make amazing drivers and stuff to add on to your video card to make it better?(better drivers than the company that makes them?? not that i could)
    SCAR Tutorials: The Form Tutorial | Types, Arrays, and Classes
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    Quote Originally Posted by dan cardin View Post
    thats awsome oo bad i dont know that guy

    so could u make amazing drivers and stuff to add on to your video card to make it better?(better drivers than the company that makes them?? not that i could)
    uh.. yes and no.

    i mean, i could learn it.. but drivers.. especialy viedo drivers.. are VERY hardware specific. It would take allot of research and study to make a driver for an nvidia card.

    and me being able to build and simulate a pipelined procesor doesnt have too many corelation to driver building..

    but there are a few, just not enough.
    [IMG]http://farm3.static.flickr.com/2120/2052732965_348f3629d0_o.jpg[/IMG]

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    im not saying u specifically, i just meant if i happened to meet someone that specialized in making drivers , weather(that spelling mean like rain? or is it right?) they could make a driver that would be able to make the video card perform better than the manufacturer's own. Though i guess thats techinically possible. So im not asking that . I am asking if you could take an old video card, something that was made for like 98's, or around then, and u made an amazing driver for it, is it possible for it to be able to display like...quake 4 or some newfangled graphics?

    EDIT: newfangled rules!! FTW!!!!!!!!!
    EDIT EDIT: that was a really long post
    EDIT EDIT EDIT: and confusing
    SCAR Tutorials: The Form Tutorial | Types, Arrays, and Classes
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    a drive is nothing more than a few simple intructions and tricks that shows the computer how to sue the hardware.

    I am nearly 100% for sure that the person who made the hardware would know how to best make the driver for it, lol.

    There will be no real "upgrades" for any driver, unless the person really didnt know what they were doing (unlikly if they created the hardware)

    all you can do is modifications (which are not normally good, like always trasparent walls, lol, they are grweat for cheating.. but not really how you want your geraphics card to always perform)

    not to mention that old cards are limited because they simply dont have the on chip support for some on the new open GL or direct x fancyness.

    not to mention that they really dont have anywhere close to the right amount of memory on the chip either.
    [IMG]http://farm3.static.flickr.com/2120/2052732965_348f3629d0_o.jpg[/IMG]

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